package deadlock

import "fmt"
import "dumpwave"
func dmux(
		decodeDmux	chan DEDM,
		registerDmux		chan REDM,
		dmuxAlu		chan DMAL) {
	for{
		dedm :=<- decodeDmux
		fmt.Println("[DMUX] Recebeu a instrucao")
		
		switch dedm.DMUX_UNIT{
			case ALU:
				switch dedm.DMUX_COMMAND{
					case RRS_RRT_WRD:
						fmt.Println("[DMUX] Recebeu RRS_RRT_WRD")
						redm :=<- registerDmux
						fmt.Println("[DMUX] Recebeu bus1 e bus2")
						dmuxAlu <- DMAL{BUS1:redm.BUS1, BUS2:redm.BUS2}
						fmt.Println("[DMUX] Enviou bus1 e bus2 p/ alu")
					
					case RRS_WRT:
						fmt.Println("[DMUX] Recebeu RRS_WRT")
						redm :=<- registerDmux
						fmt.Println("[DMUX] Recebeu bus1 e bus 2")
						dmuxAlu <- DMAL{BUS1:redm.BUS1, BUS2:redm.BUS2}
						fmt.Println("[DMUX] Enviou bus1 p/ alu")
					
					case RRS_RRT:
						fmt.Println("[DMUX] Recebeu RRS_RRT")
						redm :=<- registerDmux
						fmt.Println("[DMUX] Recebeu bus1 e bus2")
						
						dumpwave.Wave(1,"req_ack_DEDM")			//dumpWave
						dumpwave.Wave(int(redm.BUS1),"cha_DEDM")	//dumpWave
						dmuxAlu <- DMAL{BUS1:redm.BUS1, BUS2:redm.BUS2}
						dumpwave.Wave(0,"req_ack_DEDM")			//dumpWave
						fmt.Println("[DMUX] Enviou bus1 e bus2 p/ alu")
				}
		}
	}
}